BEYOND ARDUINO

Op-Amps, Comparators & Data Converters

A Study Guide

Operational Amplifiers • Comparators • Analog-to-Digital Conversion Digital-to-Analog Conversion • PWM

• Part 1 — Operational Amplifiers

• 1.1 What Is an Amplifier?

• 1.2 What Is an Op-Amp?

• 1.3 Modeling an Amplifier: The Two-Port Network

• 1.4 Dependent (Controlled) Sources

• 1.5 Inside the Op-Amp: The Internal Model

• 1.6 Ideal vs. Typical Op-Amp Characteristics

• 1.7 The 741: A Real-World Op-Amp

• 1.8 The Inverting Amplifier & Negative Feedback

• 1.9 Analyzing the Inverting Amplifier

• Part 2 — Comparators

• 2.1 What a Comparator Does

• 2.2 Comparator Examples

• 2.3 Logic-Level Mismatches & Fixing Them

• Part 3 — Analog-to-Digital Conversion (ADC)

• 3.1 Discrete vs. Continuous Data

• 3.2 The ADC Block & Encoding

• 3.3 Flash ADC

• 3.4 Successive Approximation ADC (SAR)

• 3.5 Sample and Hold

• 3.6 Digital Ramp (Staircase) ADC

• 3.7 Analog Ramp ADC (Bonus)

• 3.8 Comparing ADC Architectures

• Part 4 — Digital-to-Analog Conversion (DAC)

• 4.1 What Digital-to-Analog Conversion Does

• 4.2 Pulse Width Modulation (PWM) as a DAC

• 4.3 DAC Pinout Basics

• 4.4 The Binary-Weighted DAC

• 4.5 The R-2R Ladder DAC

Part 1 — Operational Amplifiers

1.1 What Is an Amplifier?

An amplifier is a functional block that takes in a voltage (and current) signal and produces a modified voltage (and current) signal at its output. What it modifies is the amplitude of the signal — multiplying it by some constant factor.

A voltage amplifier might take in a signal and output a version that is, say, twice the amplitude, while still preserving its shape (a sine wave stays a sine wave, just taller). If the multiplication isn't a clean constant factor, the output shape gets distorted — an undesired side effect called distortion. Amplifiers can also shift a signal in time, which shows up as a phase shift.

• Amplification: output signal is larger in amplitude than the input.

• Attenuation: output signal is smaller in amplitude than the input — still technically the job of an “amplifier” block, just with a gain less than 1.

A classic real-world example is the block diagram of an AM radio receiver (a superheterodyne receiver), which chains together a radio-frequency amplifier, an intermediate-frequency amplifier, and an audio amplifier — each one boosting the amplitude of the signal at a different stage.

1.2 What Is an Op-Amp?

Definition

An operational amplifier (op-amp) is an attempt at building an ideal amplifier block — a general-purpose building block with all the convenient characteristics an engineer could want, so that once you have one, you can design almost any amplifier circuit around it.

Op-amps are available as standalone integrated circuits (ICs), and are also embedded by the dozen inside more complex analog and digital chips — microcontrollers, TVs, phones, and so on. Well-known standalone op-amp ICs include the LM082 (built with a technique called “BiFET”) and, above all, the LM741 — by far the most popular op-amp ever made. Popular standalone comparators include the LM324 and LM339.

Op-amps are central to data converters (the subject of Parts 3 and 4 of this guide) for two reasons: they can compare voltages, and they can output an arbitrary analog voltage — exactly the two abilities needed to build analog-to-digital and digital-to-analog converters.

1.3 Modeling an Amplifier: The Two-Port Network

To analyze or design an amplifier without worrying about everything happening inside it, engineers model it as a two-port network: a black box with an input port (input voltage and current) and an output port (output voltage and current, ultimately reaching a load).

Four basic parameters describe how any two-port network behaves:

Parameter	Formula	What it Tells You
Voltage gain (Av)	Vout / Vin	How much the output voltage is multiplied relative to the input voltage
Current gain (Ai)	Iout / Iin	How much the output current is multiplied relative to the input current
Input impedance (Zin)	Vin / Iin	How much current the amplifier demands from whatever feeds it
Output impedance (Zout)	Measured via a short-circuit test at the output	How much the output voltage sags under load

Because the amplifier's internal design is usually known (you designed it, or you know its datasheet), the input and output impedance can typically be worked out directly from the internal circuitry; the voltage and current gain likewise follow from Ohm's law applied to the two-port model.

Desired Two-Port Parameters

For a genuinely useful amplifier, four things are desirable:

• High input impedance: so the amplifier draws as little current as possible from whatever stage feeds it (ideally zero).

• Low output impedance: so there's minimal voltage drop between the amplifier's internal source and the actual load — the load should see close to the full output voltage (ideally zero ohms).

• High voltage gain: the whole point of an amplifier is to control this gain and make it large.

• Flat frequency response: ideally, the amplifier performs equally well at any frequency, with no preference for low, mid, or high frequencies.

1.4 Dependent (Controlled) Sources

A two-port network's internal behavior is captured using one of four dependent (or “controlled”) source models — a source whose output value is set by some other voltage or current elsewhere in the circuit, rather than being fixed:

Model	Input → Output	Gain Symbol	Gain Units
Current-controlled current source	Current → Current	Ai	none (dimensionless)
Current-controlled voltage source	Current → Voltage	Rᵣ (trans-resistance)	ohms (Ω)
Voltage-controlled voltage source	Voltage → Voltage	Av	none (dimensionless)
Voltage-controlled current source	Voltage → Current	Gm (transconductance)	siemens / mhos

It's worth remembering where the power for these controlled sources actually comes from: the dependent source only sets the shape/value of the signal, but the energy behind it comes from the amplifier's own external DC power supply (its positive and negative supply rails), not from the small input signal itself. This is also why amplifiers can chain together in a cascade architecture, with each stage's output feeding the next stage's input, each one boosting energy along the way using its own supply.

1.5 Inside the Op-Amp: The Internal Model

Internally, an ideal op-amp is modeled as a differential voltage-controlled voltage source: it amplifies the voltage difference between its two input terminals (the non-inverting “+” input and the inverting “−” input), not the voltage of either input relative to ground.

Vin = V(+) - V(-) // the differential input
Vout = Aol * Vin // the (open-loop) internal source

Internally there's also an input resistance (which we want high) and an output resistance (which we want low), plus the positive and negative supply terminals that actually power the device. The gain here, Aol, is called the open-loop gain — “open-loop” because, at this stage, there's no external feedback path connecting the output back to the input.

1.6 Ideal vs. Typical Op-Amp Characteristics

Five characteristics define the “ideal” op-amp that engineers were chasing when the concept was developed — and modern ICs get remarkably close:

Characteristic	Ideal Value	Typical Real-World Value
Input impedance (Zin)	Infinite	Over 10 MΩ
Output impedance (Zout)	0 Ω	Well under 100 Ω (some as low as 10–50 Ω)
Open-loop voltage gain (Aol)	Infinite	10,000 to well over 1,000,000
Bandwidth / max. frequency	Infinite	Often over 100 MHz
Output when Vin = 0	Exactly 0 V	A few microvolts (very close to 0 V)

The “Infinite Gain × Zero Volts” Puzzle

If the open-loop gain is infinite, what happens when the input voltage is exactly zero? Infinity times zero is undefined — but the fifth ideal characteristic patches this: by definition, a zero-volt input must produce a zero-volt output. In practice, this near-zero-output-at-zero-input behavior is exactly what real chips exhibit (down to microvolts).

In practice, almost all circuit analysis with op-amps boils down to leaning on just two of these characteristics: the (near) infinite input impedance, and the output voltage always sitting somewhere between the positive and negative saturation voltages.

1.7 The 741: A Real-World Op-Amp

The LM741 is the most iconic standalone op-amp IC, typically packaged in an 8-pin DIP. Its pinout is simple: pins 2 and 3 are the inverting and non-inverting inputs, pin 6 is the output, and pins 7 and 4 are the positive and negative supply voltages. Notably, there is no ground pin — the “ground” reference is understood to sit midway between the positive and negative supplies. Two additional pins, labeled “offset null,” exist to correct a common op-amp imperfection when needed.

Internally, the 741's schematic is a fairly dense web of bipolar junction transistors, organized into a differential amplifier input stage (which does the actual subtracting of the two input voltages), current-mirror blocks (which copy a current from one transistor to another — a common building block in linear ICs), and an output stage. You don't need to understand every transistor to use the chip — what matters is that a lot of engineering has gone into making the finished part behave like the ideal model above.

1.8 The Inverting Amplifier & Negative Feedback

The first serious op-amp circuit worth building is the inverting amplifier. Its defining feature is a feedback resistor (Rf) connecting the output back to the inverting input — a negative feedback loop.

Why Negative Feedback Matters

Without feedback, the enormous open-loop gain would slam the output into saturation almost instantly. Negative feedback works against that: if the output starts to grow too large, more of that growth gets fed back into the inverting input, which acts to reduce the growth. The result is a stable, well-controlled output voltage instead of a saturated one.

1.9 Analyzing the Inverting Amplifier

Step 1 — High Input Impedance ⇒ Zero Input Current

Because an ideal op-amp draws (essentially) zero current into either input pin, the only current flowing into the summing node (the inverting input) is the current arriving through the input resistor, and the only current flowing out is the current heading through the feedback resistor.

Step 2 — KCL at the Summing Node

Applying Kirchhoff's Current Law at the inverting-input node (current in = current out):

I_in + I_feedback = 0 A

which rearranges to:

I_feedback = − I_in

Step 3 — The Virtual Ground Effect

For a real (finite but very large) output voltage to result from multiplying by a near-infinite open-loop gain, the voltage difference between the op-amp's two input terminals must be almost exactly zero. Since the non-inverting input is tied to ground in this circuit, that means the inverting-input node is also, for practical purposes, at 0 V — even though it isn't physically wired to ground. This is called a virtual ground.

Key Takeaway

We're allowed to use two simplifying facts together: the current flowing into either op-amp input is (essentially) zero amps, and the voltage between the two inputs is (essentially) zero volts. Together, these two facts make solving negative-feedback op-amp circuits with basic circuit analysis (Ohm's Law + KCL) surprisingly easy.

Step 4 — Solving for the Gain

With the inverting input sitting at virtual ground, the input and feedback currents can be written directly in terms of the resistor values:

I_in = Vin / Rin I_feedback = Vout / Rf

Substituting into I_feedback = − I_in and solving for Vout gives the defining equation of the inverting amplifier:

Vout = − (Rf / Rin) × Vin

This is why it's called an inverting amplifier: the output is always the negative (inverted) version of the input, scaled by the ratio of the two resistors. Want a gain of exactly 2? Simply make the feedback resistor twice the value of the input resistor. This is the elegance of the op-amp: a nearly ideal, general-purpose amplifier, configurable with just two resistors.

The Rest of the Two-Port Parameters

• Input impedance: for this circuit, simply equals Rin (the input resistor is the only path the source current has into the circuit).

• Output impedance: equals the feedback resistor Rf in parallel with the op-amp's own tiny internal output impedance. Since the internal output impedance (often just a few ohms) is so much smaller than a typical kilohm-range Rf, the combined result stays very close to the op-amp's own excellent internal output impedance.

• Current gain: depends on whatever load resistance is connected at the output — unlike voltage gain, it isn't a fixed property of the amplifier alone.

Part 2 — Comparators

2.1 What a Comparator Does

Definition

A comparator is an op-amp used open-loop (no feedback), applied to answer exactly one question: is the voltage at the non-inverting (+) input higher than the voltage at the inverting (−) input?

Because the open-loop gain is enormous, even a tiny voltage difference between the two inputs is enough to slam the output to one of its two saturation voltages:

• If V(+) > V(−): the output swings to the positive saturation voltage (“yes”).

• If V(+) < V(−): the output swings to the negative saturation voltage (“no”).

Saturation voltages sit just slightly inside the supply rails (e.g., roughly ±8.5 V on ±9 V supplies) — the exact margin depends on the specific chip and its datasheet.

2.2 Comparator Examples

Example 1 — A Potentiometer

A potentiometer (a variable resistor with a sliding contact) can produce any voltage between 0 V and its supply voltage, depending on where its knob sits. Feeding that variable voltage into a comparator's non-inverting input, alongside a fixed reference voltage on the inverting input, lets the comparator continuously answer “is the pot's voltage currently above the reference?” — producing a clean high/low digital signal from a smoothly varying analog control.

Example 2 — A Light Sensor

A phototransistor's collector current depends on how much light hits it — more light allows more current to flow. Passed through a resistor, that varying current produces a varying voltage drop: more light means a bigger drop (lower output voltage), less light means a smaller drop (higher output voltage). The result is an inverse relationship between light intensity and output voltage — but critically, it's a smoothly varying analog voltage, not yet a clean digital signal.

2.3 Logic-Level Mismatches & Fixing Them

A digital logic gate (e.g., a classic TTL gate) only recognizes two ranges reliably: below about 0.8 V reads as a logical low, and above about 2.1 V reads as a logical high. Anything in between is undefined.

The Problem

A light sensor's raw output might only swing between, say, 3 V (light) and 4 V (dark) — both comfortably above the gate's 2.1 V “high” threshold. The gate would see a permanent logical 1 no matter what the sensor actually detects, completely losing the light/dark information.

The fix is to insert a comparator between the sensor and the logic gate. Set a reference voltage roughly midway between the sensor's two extremes (e.g., 3.5 V, dialed in with a trimmer potentiometer), and compare the sensor's output against that threshold. Powering the comparator from the same supply as the logic gate (and using ground as its “negative” supply) makes its two output states land exactly on the gate's expected 0 V / 5 V logic levels — cleanly translating a fuzzy analog signal into a crisp digital one.

The resulting output plot shows a clean square wave: the comparator's output snaps low (or high) at exactly the instants the sensor's analog signal crosses the reference threshold — exactly the sharp transition a digital gate expects.

Part 3 — Analog-to-Digital Conversion (ADC)

3.1 Discrete vs. Continuous Data

	Digital Data	Analog Data
Domain	Discrete — a finite set of possible values over any given range	Continuous — an infinite set of possible values over any given range
Example	The integers: over the range 1–5, only five values exist (1, 2, 3, 4, 5)	The real numbers: over the range 1–5, infinitely many values exist (√2, √3, 2.7, …)
Plot shape	Step-like (staircase)	Smooth, continuous curve

Since the real world is analog (temperature, pressure, voltage, blood pressure, and so on all vary continuously), computers need a systematic way to represent analog values using digital (discrete) data. That process is called encoding, and it's the core job of an ADC.

3.2 The ADC Block & Encoding

An ADC has a single analog input line and multiple digital output lines — one line per bit of resolution. An n-bit ADC can represent 2ⁿ distinct output codes, evenly spaced across the ADC's reference voltage range.

• All zeros (000…0): corresponds to the ADC's minimum representable voltage (often 0 V).

• All ones (111…1): corresponds to the ADC's maximum representable voltage (set by its positive reference voltage, Vref).

• Midpoint code (100…0): corresponds to the midpoint voltage, since ADCs are typically linear.

The general encoding formula (for an n-bit ADC, ignoring rounding) is:

Code = (2ⁿ − 1) × (Vin / Vref)

For example, with a 10-bit ADC (1023 max code) and a 12 V reference, a 7 V input encodes to roughly 7 × (1023/12) ≈ 597. The smallest voltage change the ADC can detect — the weight of its least significant bit — is called its resolution.

3.3 Flash ADC

Profile

Fastest ADC architecture. Simplest, most intuitive design. But also the most hardware-hungry — it doesn't scale well to higher bit counts.

A flash ADC works by brute force: a resistor ladder divides the reference voltage into 2ⁿ evenly spaced levels, and a bank of comparators — all running in parallel — simultaneously check the input voltage against every single level.

Because a comparator (built from an op-amp) has extremely high input impedance, the resistor ladder can be treated as a simple series voltage divider, undisturbed by the comparators tapping into it. Each comparator answers “is Vin above my particular threshold?” — all at once, with no waiting, which is exactly why this architecture is so fast.

The bank of comparator outputs forms a distinctive pattern known as a thermometer code: a run of 1s followed by a run of 0s (or vice versa), where the position of the transition — not a standard binary count — indicates the level. A priority encoder circuit then converts that thermometer code into an ordinary binary number, simply by finding the highest level at which the code transitions.

Why Flash ADCs Don't Scale

A flash ADC needs one comparator per voltage level boundary — that's (2ⁿ − 1) comparators for an n-bit converter:

Resolution	Comparators Required
3 bits	7
8 bits	255
12 bits (industry standard)	4,095
16 bits	65,535

Each comparator is itself a small circuit of several transistors, so the component count explodes rapidly with resolution. Flash ADCs remain unbeatable for raw speed, but the cost in silicon area, materials, and power consumption makes them impractical at high bit depths — which is exactly why they aren't the popular choice in general-purpose designs.

3.4 Successive Approximation ADC (SAR)

Profile

The most popular ADC architecture by far — not the absolute fastest, but one of the fastest, and dramatically more efficient in hardware than a flash ADC. This is very likely the ADC built into your microcontroller.

The Closed-Loop Structure

A SAR ADC works by comparing the input voltage against the output of an internal DAC (yes — building an ADC requires a DAC!). A comparator checks whether the input is higher or lower than the DAC's current guess, and feeds that yes/no answer back into a Successive Approximation Register (SAR) — a sequential state machine, clocked, that keeps refining the guess.

Vin → [Comparator] → SAR (state machine) → [DAC] → feeds back into Comparator

The Algorithm — A Worked Example

Consider a 4-bit SAR ADC with a 12 V reference and a 10 V input. Each bit weighs half of the previous bit's weight: the most significant bit (MSB) is worth 6 V, the next is worth 3 V, then 1.5 V, then 0.75 V.

• 1. Test the MSB: guess 1000 (6 V). Is 10 V > 6 V? Yes → keep the 1. Current guess: 1000.

• 2. Test the next bit: guess 1100 (6 + 3 = 9 V). Is 10 V > 9 V? Yes → keep the 1. Current guess: 1100.

• 3. Test the next bit: guess 1110 (6 + 3 + 1.5 = 10.5 V). Is 10 V > 10.5 V? No → clear the bit. Current guess: 1100.

• 4. Test the last bit: guess 1101 (6 + 3 + 0.75 = 9.75 V). Is 10 V > 9.75 V? Yes → keep the 1. Final code: 1101.

After the last bit is tested, the SAR raises an End-of-Conversion (EOC) signal, telling the rest of the system (e.g., a microcontroller) that the register now holds a stable, correct result ready to be read.

Why It's Just Binary Search

Each iteration narrows the range of possible voltages by half — exactly the logic of the binary search algorithm, just running in the analog world instead of over a sorted array. That's why a SAR ADC needs only n comparison cycles for an n-bit result: for a 10-bit ADC, that's just 10 cycles to pick the correct value out of 1,024 possibilities, no matter how large the array (or, here, the voltage range) is.

A Useful Contrast: Sequential Search

Replacing the SAR with a plain counter (incrementing the DAC's guess by one step at a time, checking each time) is the equivalent of a sequential search: it always finds the right answer, but can take up to 2ⁿ − 1 cycles in the worst case, and its running time grows linearly (O(n) in the value, not the bit count) rather than logarithmically. This is dramatically slower for anything beyond a few bits, which is exactly why the SAR's binary-search approach wins in practice.

3.5 Sample and Hold

Because a SAR conversion takes several clock cycles to complete, the input voltage needs to stay perfectly still for the whole conversion — otherwise, a changing input partway through would corrupt the higher-order bits that were already locked in. A Sample-and-Hold block solves this by taking an instantaneous “snapshot” of the input voltage and holding it steady for the ADC to work with.

A Simple Implementation

A voltage follower (unity-gain buffer) first re-buffers the input with a very high input impedance, drawing negligible current. That buffered voltage then passes through an analog switch into a capacitor. Sending a logical 1 (“go”) closes the switch, letting the capacitor charge up to match the input voltage. Sending a logical 0 opens the switch, and the capacitor — with nowhere for its charge to go — holds that voltage steady, regardless of any subsequent changes at the input, for as long as the conversion takes.

3.6 Digital Ramp (Staircase) ADC

A simpler (and much less efficient) alternative to the SAR is the digital ramp, or staircase, ADC — essentially a SAR ADC with the register replaced by a plain up-counter. The counter increments one step at a time, and the internal DAC's output climbs in a staircase pattern until it just exceeds the input voltage, at which point the counter stops and signals end-of-conversion.

Complexity Comparison

The staircase ADC's running time is linear in the number of representable values — O(2ⁿ) in the worst case — exactly like a sequential search. The SAR ADC, using essentially identical circuit complexity (both are simple state machines, similarly sized), instead runs in O(n) — logarithmic in the number of representable values. Since the SAR is no harder to build than the staircase counter, there's little reason to ever prefer the staircase design in practice.

3.7 Analog Ramp ADC (Bonus)

A variation on the staircase idea replaces the digital counter entirely with an analog ramp generator (a voltage that rises linearly over time, produced with a transistor-and-capacitor circuit) and a pair of comparators. One comparator asks “is the ramp still below the input voltage?” and the other asks “is the ramp currently positive?” — together, these two answers open a logical time window during which a fixed-frequency clock signal is allowed to pass through an AND gate into a counter.

The number of clock pulses the counter accumulates during that open window is directly proportional to how long the ramp took to reach the input voltage — which is itself proportional to the input voltage. In effect, this circuit converts a voltage into a time interval, and then converts that time interval into a digital count.

This design is not particularly efficient: a large portion of each ramp cycle (the negative half, and any time after the input has already been exceeded) is simply wasted, contributing nothing to the measurement. It's included here mainly to illustrate how a closed-loop ADC can be built out of continuous-time, rather than digital, building blocks.

3.8 Comparing ADC Architectures

Architecture	Speed	Circuit Complexity	Typical Cycles
Flash ADC	Fastest (parallel)	Very high — (2ⁿ − 1) comparators	1 (all at once)
Successive Approximation (SAR)	Fast	Low — one comparator, one DAC, a small state machine	n (one per bit)
Digital Ramp / Staircase	Slow	Low — similar to SAR, but a counter instead of a SAR register	Up to 2ⁿ − 1 (worst case)

Bottom Line

Analog-to-digital conversion is both possible and efficient, and there's a real design trade-off between speed and circuit complexity. The successive approximation ADC wins as the most popular real-world choice because it strikes the best balance: much faster than a staircase ADC, and far simpler (and cheaper) than a flash ADC.

Part 4 — Digital-to-Analog Conversion (DAC)

4.1 What Digital-to-Analog Conversion Does

A DAC takes in a digital code (an encoding of some value, sampled at discrete moments in time) and produces the corresponding analog voltage at its output. Because the original signal is only ever captured at discrete sampling instants, the DAC's raw output looks like a “staircase” approximation of the original waveform — it can only output one sampled value at a time, held until the next sample arrives.

Feeding that staircase output through a low-pass filter smooths out the sharp steps, producing a much closer (if slightly delayed) approximation of the original continuous signal.

As with ADCs, the digital code follows a fixed-point binary interpretation: the most significant bit represents one-half of the reference voltage, the next bit one-quarter, the next one-eighth, and so on — each bit worth exactly half its left neighbor.

4.2 Pulse Width Modulation (PWM) as a DAC

PWM is arguably the simplest way to get an “analog-like” output from a purely digital system: instead of varying a voltage directly, you vary the duty cycle — the fraction of each fixed-length period that a digital signal spends high.

• 15% duty cycle: signal is high for 15% of each period — a connected LED, for instance, would appear dim.

• 50% duty cycle: signal is high half the time — medium brightness.

• 75% duty cycle: signal is high most of the time — noticeably brighter.

For this to look smooth and “analog” to a human observer (or a motor, or a filter), the PWM frequency needs to be high enough that individual pulses aren't perceptible — anything above about 30 Hz works, though 1 kHz is a common practical choice. The duty cycle itself is set by loading a binary number into a timer (e.g., loading the binary encoding of “75” sets a 75% duty cycle out of a period of 100 counts).

Passed through a simple low-pass filter, a PWM signal's average value becomes a genuinely smooth analog voltage that tracks the duty cycle. This matters in practice because many microcontrollers (including the classic Arduino) have no true DAC on board at all — the Arduino's analogWrite() function is, under the hood, just PWM.

4.3 DAC Pinout Basics

A typical DAC has one digital input pin per bit of resolution (4 pins for a 4-bit DAC, 10 pins for a 10-bit DAC, and so on), plus a reference voltage input (Vref) that sets the maximum output voltage. All bits at 1 corresponds to the maximum output (set by Vref); all bits at 0 corresponds to the minimum (usually 0 V). Some DACs support a differential reference input, allowing both positive and negative output voltages instead of only positive ones.

4.4 The Binary-Weighted DAC

The most direct DAC implementation is a summing amplifier (an op-amp inverting amplifier with multiple input resistors) combined with a set of digitally controlled analog switches — one per input bit. Each switch connects its resistor either to ground (bit = 0) or to the reference voltage (bit = 1).

The key trick is weighting: by giving each input resistor a different value relative to the feedback resistor, each bit contributes a different fraction of the reference voltage to the output sum. For a 4-bit binary-weighted DAC:

Vout = − (½·D3 + ¼·D2 + ⅛·D1 + ¹⁄₁₆·D0) × Vref

where each Di is either 0 V or Vref, depending on its switch position. The weighting is achieved by setting the input resistor for the MSB to 2× the feedback resistor, the next bit's resistor to 4×, the next to 8×, and so on — doubling for every less-significant bit. Because the summing-amplifier configuration inherently inverts the sign, a following unity-gain inverting stage is typically added to restore the correct polarity.

The Scaling Problem

This design becomes impractical fast. An 8-bit version needs a resistor 256× the feedback resistance for its least significant bit; a 12-bit version needs one 4,096× the feedback resistance. Manufacturing a wide spread of precise resistor values — especially very large ones — gets difficult and expensive very quickly.

4.5 The R-2R Ladder DAC

The R-2R ladder network solves the binary-weighted DAC's scaling problem elegantly: instead of needing a huge range of different resistor values, it uses only two resistor values throughout — R and 2R — no matter how many bits the DAC has.

The ladder structure repeats a simple pattern (2R, R, 2R, R, 2R, …, ending in 2R) and produces mathematically the same weighted-sum behavior as the binary-weighted design, once fed into an op-amp with a feedback resistor Rf = R.

How the Analysis Works (Thévenin Reduction)

The ladder can be analyzed bit by bit using repeated Thévenin equivalents, working from the far end of the ladder back toward the op-amp input:

• 1. Two resistors of value 2R in parallel reduce to a single resistor of value R.

• 2. That R in series with the ladder's next R rung combines back up to 2R.

• 3. This pattern repeats down the whole ladder — at every stage, the “seen” resistance to ground from any node is always exactly R or 2R, which is what makes the ladder so elegant.

• 4. Working through a full Thévenin reduction collapses the entire network, for any given input code, down to a single equivalent voltage source and a single 2R series resistance feeding the op-amp's input.

For example, feeding the code 1000 into a 4-bit R-2R ladder reduces (after the Thévenin analysis) to an equivalent source of Vref/2 in series with a resistance of R, driving an inverting amplifier with unity gain (since Rf = R). The result is:

Vout = − (Vref / 2) × (− 1) = + Vref / 2

— exactly the expected result, since the MSB of a 4-bit code is defined to represent one-half of the reference voltage.

R-2R DAC Advantages

• Only two resistor values needed: just R and 2R, regardless of the DAC's bit count — no more chasing down exotic, precisely-scaled resistor values.

• Very fast: there's no sequential logic or iteration involved — the circuit is purely resistive plus one op-amp, so a change in the digital input appears at the output almost immediately, limited mainly by the op-amp's slew rate.

• Small circuit: the whole converter needs only a bank of resistors and a single op-amp — far more compact than a flash-ADC-style approach.

Because of these advantages, R-2R ladders are the resistive DAC architecture of choice inside many real integrated circuits, including some SAR ADCs that use an internal R-2R DAC as part of their feedback loop (see Part 3).

Quick-Reference Summary

Concept	One-Line Takeaway
Amplifier	A block that multiplies a signal's amplitude by a constant factor
Op-amp	A near-ideal, general-purpose amplifier IC: huge gain, huge Zin, tiny Zout
Negative feedback	Feeding part of the output back to the inverting input stabilizes the gain
Virtual ground	With feedback, the op-amp's input voltage difference is forced to ≈ 0 V
Inverting amp gain	Vout = −(Rf / Rin) × Vin
Comparator	An open-loop op-amp: answers “is V(+) higher than V(−)?” with a saturated output
ADC	Converts a continuous analog voltage into a discrete digital code
Flash ADC	Fastest, but needs (2ⁿ − 1) comparators — doesn't scale to high resolution
SAR ADC	Most popular; performs a binary search using a DAC + comparator, n cycles
Sample & Hold	Freezes the input voltage steady for the duration of a conversion
DAC	Converts a digital code into the corresponding analog voltage
PWM	A simple digital-to-analog trick: vary duty cycle, then low-pass filter
Binary-weighted DAC	Summing amplifier with doubling resistor values — doesn't scale well
R-2R ladder DAC	Same result as binary-weighted, using only two resistor values (R, 2R)

Thursday, August 6, 2026

BEYOND ARDUINO

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