Thursday, October 8, 2026

How to Select and Calculate a Heatsink for an IC, MOSFET, or Other PCB Component

A heatsink must provide low enough thermal resistance to keep the junction temperature below a safe limit. Wattage or physical size alone won't tell you what to buy. You need to know how much heat is generated, how hot the part may get, and how easily heat travels from the silicon to the air.

1. The heat-flow path

Treat heat flow like current through series resistors, with temperature difference as the voltage. Heat passes through:

1. Junction (the die), at T_J.

2. Case, crossed with R_θJC (from the datasheet).

3. Thermal interface (grease, pad, insulator), R_θCS.

4. Heatsink, R_θSA.

5. Ambient air, at T_A.

Resistances are in °C/W (K/W). A poor interface can ruin an otherwise good heatsink.

Limits of the series model: it assumes essentially all heat leaves through the case, interface, and heatsink. Many packages also shed heat through other paths in parallel, such as leads and PCB copper (a TO-220's leads, or an SMD part cooled from both the board and a top-mounted sink). Ignoring these makes the estimate conservative, but for such devices the simple series model may not capture the full thermal behavior. Use the manufacturer's thermal model where one is given.

2. Step 1: Find the power dissipated as heat

Use the power lost inside the component, not the power delivered to the load.

MOSFET conduction loss:

P_cond = I_D² × R_DS(on)

Use R_DS(on) at your actual gate-drive voltage and operating junction temperature, not the 25 °C headline value. Check the datasheet's resistance-versus-temperature curve. Hot values are often 1.5 to 2 times higher. At 5 A with 0.04 Ω at 25 °C, the loss is 1.0 W. If the hot value is 0.064 Ω, it is 1.6 W, which is 60% higher than the cold estimate. Designing around the cold figure significantly underestimates the heat.

MOSFET switching loss (first-order estimate):

P_sw ≈ ½ × V_DS × I_D × (t_r + t_f) × f_sw

This assumes idealized linear transitions. Real losses depend on the actual voltage and current waveforms, gate resistance, parasitic capacitances, reverse recovery, and load type (inductive loads usually cost more). Body-diode conduction and reverse-recovery losses may also apply.

Output-capacitance loss:

P_oss ≈ E_oss × f_sw

C_oss varies strongly with drain voltage, so the simple ½ × C_oss × V² × f_sw form is only a rough guide. Where the datasheet gives the stored energy E_oss (at or near your operating voltage), use it instead.

Gate-drive power:

P_g ≈ Q_g × V_GS × f_sw

This is the power needed to charge and discharge the gate each second. It is dissipated across the driver's output stage and the gate resistor, not only in the driver. It matters for driver heating but is usually small for the MOSFET's own heatsink. At high frequency, rely on the manufacturer's loss tools or measured waveforms.

Linear regulator or linear IC:

P_D ≈ (V_IN − V_OUT) × I_OUT + V_IN × I_Q

Example: 12 V to 5 V at 0.2 A with 5 mA quiescent current gives 1.4 + 0.06 = 1.46 W. This form is valid when I_Q is the additional ground/quiescent current drawn from the input. Datasheets don't all define current the same way, so verify the definition. For a regulator with significant ground-pin current, or one whose quiescent current varies with load, use the actual input and output currents:

P_D = V_IN × I_IN − V_OUT × I_OUT

Other parts: resistors dissipate I²R or V²/R. BJTs dissipate roughly V_CE × I_C plus base-drive and switching losses. For a switching converter, use the switching device's actual losses, not the load power.

3. Step 2: Find the maximum allowable heatsink resistance

T_J = T_A + P_D × (R_θJC + R_θCS + R_θSA)

Solving for the heatsink:

R_θSA ≤ (T_J,target − T_A) / P_D − R_θJC − R_θCS

Choosing the target: don't design to the absolute maximum (often 150 or 175 °C). Typical derated targets are 100 to 125 °C for commercial designs and 80 to 100 °C for high-reliability or hot-environment equipment. Use the worst-case air temperature near the part, not room temperature.

Typical R_θCS (approximate; depends on package, contact area, interface thickness, and clamping pressure):

• Grease on a flat, clamped surface: about 0.1 to 0.5 °C/W.

• Silicone pad: about 0.5 to 1.5 °C/W.

• Mica insulator plus grease: about 1 to 3 °C/W or more.

Worked example: MOSFET at 3 W

Assume 3 W (hot R_DS(on) included), 40 °C worst-case ambient, 150 °C absolute maximum, 110 °C design target, R_θJC = 2 °C/W, and R_θCS = 0.5 °C/W.

At the absolute maximum:

R_θSA ≤ (150 − 40) / 3 − 2 − 0.5 = 36.67 − 2.5 = 34.17 °C/W

At the design target, which is the number to use:

R_θSA ≤ (110 − 40) / 3 − 2 − 0.5 = 23.33 − 2.5 = 20.83 °C/W

Real-world conditions. Published heatsink ratings are measured under specific conditions (airflow, orientation, temperature rise), and performance in an enclosure is often worse. Use the manufacturer's thermal curves for your actual conditions where available. Otherwise apply an engineering margin and verify by testing. For illustration only, assume a 25% penalty (an assumption, not a universal factor):

20.83 / 1.25 ≈ 16.7 °C/W

A 15 °C/W heatsink passes this check. With the assumed penalty its effective resistance is 18.75 °C/W:

T_J = 40 + 3 × (2 + 0.5 + 18.75) = 103.75 °C

At exactly 15 °C/W, T_J = 92.5 °C. Either way it is under the 110 °C target.

Practical check. Under the same assumptions, the predicted case temperature is:

T_C = T_A + P_D × (R_θCS + R_θSA) = 40 + 3 × (0.5 + 18.75) = 97.75 °C

This is valid only for the assumed steady-state model and measurement location. When comparing against a measurement:

• Measure at the defined case reference point (usually where the datasheet specifies R_θJC, such as the tab or exposed pad), with good thermal contact for the probe.

• Wait for thermal equilibrium before reading.

• Remember the junction is hotter than the case by P_D × R_θJC, so a measured case temperature must be converted using the actual power and thermal path.

A measured value well above prediction means the real dissipation or the mounting is worse than assumed.

4. Components mounted directly on a PCB

Through-hole (TO-220, TO-247): attach a heatsink to the tab. Check whether the tab is a live terminal (drain, collector); if so, an insulator is needed, which raises R_θCS.

SMD (SO-8, DPAK, PowerPAK, QFN): heat flows mainly into PCB copper. Three datasheet parameters matter:

• R_θJA: junction-to-ambient under a specified test board and setup. It is board-dependent and valid only for similar boards.

• R_θJC: junction-to-case (or to the exposed pad).

• R_θJB: junction-to-board, where specified.

Adding an external heatsink does not make the datasheet R_θJA apply; use R_θJC plus the external path instead. For PCB-cooled parts, follow the manufacturer's recommended pad layout and thermal guidance. Cooling is improved by:

• More copper connected to the thermal pad or power terminal.

• Thermal vias under the exposed pad (effectiveness depends on pad geometry, via size and count, and layer stack-up).

• Thicker copper where practical.

• Airflow and spacing from other hot parts.

5. Choosing the physical heatsink

Compare candidates by published R_θSA under conditions like yours. Rough natural-convection guides: small TO-220 clip-ons are about 20 to 30 °C/W or worse, medium extrusions about 5 to 10 °C/W, and large finned sinks a few °C/W. These are illustrations only. Check:

1. Natural vs. forced convection (a fan-rated figure needs the fan).

2. Fin orientation (vertical fins suit natural convection).

3. Worst-case local ambient inside the enclosure.

4. Mounting interface: flatness, compound, and clamping pressure.

5. Electrical isolation from live terminals.

6. Multiple devices on one sink: add their powers for R_θSA, then check each junction separately with its own R_θJC and interface.

7. Neighboring heat sources.

A heatsink's wattage rating alone isn't enough. The relevant spec is thermal resistance under conditions representative of your installation.

6. Pulsed and transient loads

A steady-state calculation alone does not establish that a pulsed condition is safe. For pulses shorter than the time needed to reach thermal equilibrium, the junction rise can be lower than the steady-state prediction. Use the datasheet's transient thermal impedance Z_θJC(t) to estimate peak junction temperature. For repetitive pulses, account for pulse width, duty cycle, and residual heat from preceding pulses; at high duty cycles the result approaches steady state. Also check the safe operating area (SOA) and pulsed-power limits.

7. A warning about datasheet ratings

A part rated for 50 W maximum dissipation cannot necessarily dissipate 50 W on your board. That figure usually assumes the case is held at 25 °C by an ideal heatsink. Your real limit depends on your ambient, thermal path, and junction target.

Quick recipe

1. Find P_D at hot operating conditions, including switching losses.

2. Choose worst-case T_A and a derated T_J target.

3. Look up R_θJC; estimate R_θCS from your mounting method.

4. Compute R_θSA,max = (T_J,target − T_A) / P_D − R_θJC − R_θCS.

5. Account for real-world conditions using manufacturer thermal data where available; otherwise, apply an appropriate engineering margin and verify by testing.

6. Measure case temperature at a defined point under worst-case operation, after reaching thermal equilibrium, and compare it with your prediction.

Friday, October 2, 2026

Logic IC-Based Turn Signal / Hazard Flasher (CD4001 Quad-NOR)

This one is a proper automotive-style indicator (turn signal) and hazard flasher, built around a CD4001 quad NOR gate instead of discrete transistors. It drives two external lamp outputs independently (left/right), with built-in hazard (both-sides) mode and dashboard tell-tale LEDs. Here's the full breakdown.

Power Input Block: PWR + D3 + C2/C3

PWR (2-pin WAGO terminal) is the main 12V input: pin -1 is the incoming +12V, pin -2 is GND.
D3 (1N4004) sits in series right after PWR's +12V pin, acting as a reverse-polarity protection diode — unlike your earlier boards, this one actually has that protection built in.
After D3, the rail becomes the regulated logic supply (VDD) for IC1, filtered by C3 (1000µF/16V, bulk) and C2 (0.1µF, high-frequency bypass), both sitting between this VDD node and GND.

So the CD4001 runs directly off the ~12V automotive rail (minus one diode drop), which is well within its normal operating range, with the two capacitors keeping that rail clean against alternator noise and switching transients from the lamps.

Oscillator Block: IC1 gates A & B + R1 (1M) + R2 (680k) + C1 (0.68µF)

IC1 gates A and B are each wired with their two inputs tied together, turning each into a simple logic inverter. Combined with R1, R2, and C1 cross-connected between them, this forms the classic two-NOR-gate relaxation oscillator — the same role the 555 or the cross-coupled transistor pair played in your earlier flasher circuits, just done with CMOS logic gates.

Gate A inverts its input and feeds gate B.
R1/R2/C1 form the RC feedback network that continuously charges and discharges, flipping gate A's input once the threshold is crossed.
Gate B's output is the oscillator's usable output — a continuous square wave whose frequency is set by R1, R2, and C1 (roughly in the ~1 second per half-cycle range with these values, in the right ballpark for a turn-signal blink rate).

Left/Right Steering Logic: IC1 gates C & D + R3/R4 (10k) + D1/D2 + LEFT-RIGHT-SW

Gates C and D are each wired as true 2-input NOR gates (inputs not tied together this time):

One input on each (I0) is the oscillator output from gate B.
The other input (I1) is a "enable" line — gate C's I1 comes from R3/D2/the LEFT-RIGHT-SW connector pin -1; gate D's I1 comes from R4/D1/the switch's pin -3.
R3 and R4 (10k) pull these enable lines up to VDD by default — so with no switch connection, both inputs sit HIGH, forcing both gate outputs LOW (a NOR gate's output is only HIGH when both inputs are LOW). No flashing happens on either side at rest.
LEFT-RIGHT-SW is a 3-pin switch (common pin -2 tied to GND) that, when flipped left or right, grounds either pin -1 or pin -3. Grounding one of these pulls that gate's I1 LOW, which lets the oscillator's signal pass through that gate (acting as an inverter of the oscillator when enabled) — so only the selected side blinks.

D1 and D2 are diode-ORs sitting between each switch line and a shared hazard node (explained next) — they let the hazard switch pull either line low independently, without the two switch inputs fighting each other.

Hazard Block: HAZARD-SW

HAZARD-SW (2-pin) connects its pin -2 to GND, and pin -1 to the shared cathode node of D1 and D2. When the hazard switch is closed, it pulls that shared node to GND, which — through D1 and D2 — drags both gate C's and gate D's enable lines low at once, regardless of what the LEFT-RIGHT-SW is doing. That enables both steering gates simultaneously, so both sides flash together at the oscillator rate — your 4-way hazard function.

Dashboard Indicator LEDs: LED1/R5 and LED2/R6

Gate C's output feeds R5 (1k) in series with LED1; gate D's output feeds R6 (1k) in series with LED2. These are simple dash-panel tell-tale LEDs that blink in sync with whichever side is active — pure visual feedback, not part of the switching path to the lamps.

Pre-Driver Transistors: Q1/Q2 (BC547) + R9/R10 (1k)

Gate C's output also drives Q1's base through R9; gate D's output drives Q2's base through R10. Q1 and Q2 are small NPN transistors with their emitters at GND, so when a gate output goes HIGH, the corresponding transistor turns on and pulls its collector down toward GND.

Power Driver Transistors: U$1/U$2 (2SB507, PNP) + R11/R12 (1k) + R7/R8 (680k)

Q1's collector feeds U$2's base through R11; Q2's collector feeds U$1's base through R12.
U$1 and U$2 are PNP power transistors with their emitters tied straight to the diode-protected +12V rail — so they act as high-side switches. When Q1/Q2 pulls the PNP's base down, the PNP turns on and connects +12V through to its collector.
R7/R8 (680k) sit as pull-ups from +12V to each PNP's collector/lamp node. Given the high value, these aren't meant to drive the lamp on their own — they're there to bleed the output node cleanly back up to +12V when the PNP switches off, which helps avoid a faint "ghost glow" if the connected lamp is an LED-type indicator bulb with its own internal electronics that could otherwise hold a small residual voltage.

Lamp Outputs: LIGHT-1, LIGHT-2 (WAGO terminal blocks)

Both use the same WAGO 2-pin footprint as the other connectors — these are where your actual external indicator lamp/bulb modules connect.

LIGHT-1 pin -1 → U$1 collector (switched +12V); pin -2 → GND.
LIGHT-2 pin -2 → U$2 collector (switched +12V); pin -1 → GND.

So each lamp module sits between its switched 12V output and ground — standard high-side lamp switching, same pattern as your earlier LED-module flasher but through a PNP power stage instead of a MOSFET directly.

How it all works together

+12V comes in through PWR, passes through the reverse-protection diode D3, and is filtered by C2/C3 to form a clean logic supply for IC1.
Gates A and B, with R1/R2/C1, free-run as a relaxation oscillator, continuously producing a square wave at the flasher rate.
Depending on LEFT-RIGHT-SW's position, either gate C or gate D has its "enable" input pulled low, letting the oscillator signal pass through that one gate only.
That gate's pulsing output does two things at once: blinks the matching dashboard LED (LED1 or LED2), and toggles its pre-driver NPN (Q1 or Q2).
The NPN pulls the corresponding PNP's base low each time it turns on, switching that PNP (U$1 or U$2) on and off in sync with the oscillator.
The PNP, acting as a high-side switch, connects +12V to its LIGHT-1/LIGHT-2 output terminal each time it's on — flashing the external lamp in time with the oscillator, on whichever side was selected.
If HAZARD-SW is engaged, it grounds the shared node behind D1/D2, which forces both gate C's and gate D's enable lines low together — so both sides flash in unison, independent of the left/right switch position.

Points worth checking

R1/R2/C1 set the flash rate — if it comes out slower or faster than you want once tested, these are the three values to tweak (increasing C1 or the resistors slows it down, decreasing speeds it up).
D1/D2 need to be oriented so current can flow from the switch lines toward the hazard node (not the other way) — worth double-checking polarity on the physical board matches the diode-OR function described above.
The 2SB507 is an older PNP power transistor — worth confirming its current rating comfortably covers whatever bulb/lamp module you're driving (especially if it's an incandescent bulb with a higher inrush current than an LED module).
R7/R8 at 680k is a very light bleeder current — fine for LED modules, but if you ever drive an incandescent bulb directly off this output, that pull-up won't meaningfully affect it either way.

demo and files :

https://www.youtube.com/watch?v=EoGe26Is09A
direction indicator lamps.(signal light)

Cross-Coupled Astable MOSFET LED Flasher (2-Channel)

This is a self-oscillating, cross-coupled two-transistor astable multivibrator, built with MOSFETs instead of the more common BJT version, driving two alternating 12V LED modules. Here's the full block-by-block walkthrough.

Power Input Block: PWR (2-pin terminal block)

The PWR part uses a WAGO-style 2-pin terminal block (W237-102) as the DC power entry point for the whole circuit.

PWR pin -1 → GND
PWR pin -2 → +12V rail

There's no series protection diode and no bulk filtering capacitor on this rail, so getting the polarity right when wiring the supply in matters, and a reasonably stiff 12V source is a good idea since both LED modules switch on and off through this same rail.

Switching Transistors: Q1, Q2 (50N03)

Two logic-level N-channel MOSFETs do the switching.

Q1 source and Q2 source are both tied to GND.
Q1 drain and Q2 drain each feed one LED module (through L2 and L1 respectively — see below) and also feed into the cross-coupling network.

Only one of the two is ever conducting at a time, which is what gives you the alternating flash between the two LED modules.

Timing Bias Resistors: R1, R2 (10MΩ each)

R1 connects Q1's gate directly to Q1's own drain.
R2 connects Q2's gate directly to Q2's own drain.

These play the same role the base resistors play in a classic two-transistor LED flasher: when a MOSFET is off, its drain sits near +12V, so a small trickle current leaks back through this resistor into its own gate. That's what nudges the circuit into starting oscillation at power-up, and together with C1/C2 it also sets how long each half of the cycle lasts.

Cross-Coupled Timing Capacitors: C1, C2 (0.1µF each)

C1 connects Q2's drain to Q1's gate.
C2 connects Q1's drain to Q2's gate.

This cross-coupling is what turns two simple switches into an oscillator. When one MOSFET's drain falls (as it turns on), that falling edge is coupled through to the other MOSFET's gate, forcing it off. When that drain later rises back toward +12V, the rising edge couples back the other way and turns the other MOSFET on — and so on, continuously.

The R × C time constant here is roughly 10MΩ × 0.1µF ≈ 1 second, which sets the rough on-time for each MOSFET (and its LED) before the circuit flips — a slow, clearly visible blink rate rather than a fast flicker.

LED Module Connections: L1, L2 (WAGO terminal blocks)

L1 and L2 use the same WAGO 2-pin terminal block footprint as PWR, but here they're simply the external wiring points for your two 12V LED modules — not coils.

L2 pin -1 → Q1 drain
L2 pin -2 → +12V
L1 pin -1 → Q2 drain
L1 pin -2 → +12V

So each LED module sits between +12V and one MOSFET's drain. When that MOSFET turns on, it pulls its drain toward GND, which puts the full 12V across that LED module and lights it. When that MOSFET turns off, its drain floats back up toward +12V, dropping the voltage across the LED module to ~0 and turning it off.

How it all works together

At power-up, both MOSFET drains sit near +12V (pulled up through their respective LED modules), so both LEDs are briefly off or dim.
The 10MΩ R1/R2 resistors leak a trickle of bias current into each gate. Due to small component or threshold differences between the two MOSFETs, one of them (say Q1) crosses its turn-on threshold first.
Q1 turning on pulls its drain toward GND — lighting LED module L2 (connected to Q1's drain). That falling edge couples through C2 to Q2's gate, holding Q2 firmly off, so L1's LED stays dark.
C1 (connected from Q2's drain, which is now near +12V, to Q1's gate) keeps charging through R1/C1's time constant. After roughly a second, this bleeds Q1's gate voltage down enough that Q1 starts turning off.
As Q1 turns off, its drain rises back toward +12V, dimming L2's LED. That rising edge couples through C2 to Q2's gate, turning Q2 on — which pulls Q2's drain low and lights L1's LED, while also turning Q1 fully off via C1.
The cycle then repeats in reverse, with the two LED modules alternating on/off roughly once per second (per R × C), indefinitely.

Points worth checking, given you're using 12V LED modules

Since your LED modules already have the current-limiting built in (as pre-wired 12V modules usually do), driving them straight from +12V through the MOSFET drain-to-source path should be safe as-is — you don't need an extra series resistor on this board.
There's still no bulk/filter capacitor on the +12V input and no reverse-polarity protection, same as noted before — worth keeping in mind if the LED modules draw any significant inrush current when they switch on, since nothing on this board is smoothing the rail.
If you ever swap to bare LEDs (no built-in resistor) instead of modules, you'd need to add series resistors at that point — the circuit itself has no current limiting of its own for an LED.

demo and files :

https://www.youtube.com/watch?v=VTcNJ9suL1E
simple flasher (සරල flasher පරිපථය) .

Saturday, September 26, 2026

4047 Inverter

Power input block: U$1 connector
The raw DC supply comes in on this 2-pin connector. Pin P1 goes straight onto the main unregulated rail (feeding the transformer center tap, the regulator input, and the two bulk caps); pin P0 is the common ground return. As with the dimmer board, there's no series/reverse-protection diode here — correct polarity matters.

Bulk filtering: C2 + C3 (3300µF/35V each, in parallel)
Sitting across the raw rail (positive to the input node, negative to ground), these absorb the large pulsed currents the output MOSFETs pull from the supply every time they switch, keeping the center-tap rail from sagging or ringing hard at each transition.

Regulated supply block: IC2 (78XXS, populated as 7809) + R2 (220R)
IC2 drops the raw input down to a clean 9V. Rather than feeding IC1's VDD directly, the regulator's output goes through R2 (220R) first — a small series resistor into the 4047's supply pin. Notably, there's no local bypass/decoupling capacitor sitting right at IC1's VDD pin in this design (C2/C3 are the only caps on that side, and they're on the raw rail, not the regulated one) — worth keeping in mind since this rail sits next to a hard-switching power stage.

Oscillator block: IC1 (CD4047) + R1 (1k) + R4 (10k trimmer) + C1 (0.47µF)
C1 connects directly across the chip's C and R/C pins (the timing cap). The timing resistor is R1 in series with R4, run between the R and R/C pins — and R4's wiper is shorted back to one end, so like the dimmer board's trimmer, it's wired as a simple adjustable two-terminal resistor rather than a true potentiometer divider. R4 is the frequency-trim knob. The chip's AST/!AST/-T pins are tied together, and RES/RET/+T/VSS are all tied to ground — the standard hookup that puts the 4047 into continuous free-running astable mode (no external trigger). It free-runs and puts out two complementary square waves on Q and !Q.

Push-pull driver stage: Q1/Q3 + R5, and Q2/Q4 + R6
Each 4047 output feeds a discrete complementary buffer rather than driving the power MOSFETs directly. Q drives Q1 (NPN, SS8050) and Q3 (PNP, SS8550) through the shared 10R base resistor R5; !Q drives Q2/Q4 the same way through R6. In each pair, the NPN's collector sits on the raw +rail and the PNP's collector sits on ground, with both emitters tied together as the output node — a classic discrete totem-pole buffer, needed because the 4047's own outputs can't source/sink enough current to slew the power MOSFETs' gate capacitance quickly.

Gate-drive block: R7–R10 (10R each) + R11/R12 (10k each)
Each power MOSFET gets its own series gate resistor (R7→Q5, R8→Q6, R9→Q7, R10→Q8) even though the MOSFETs are paralleled in pairs — correct practice, since it damps ringing and stops parasitic oscillation between paralleled devices sharing one driver node. R11 and R12 are shared 10k pulldowns on each pair's gate node, holding the MOSFETs off if the driver stage output is ever floating.

Power switching / output stage: Q5+Q6 and Q7+Q8 (IRF3205) + TERM1/TERM2/TERM-CT
Q5 and Q6 are paralleled (drains tied together, sources tied to ground) and their common drain feeds TERM2. Q7 and Q8 are paralleled the same way, feeding TERM1. TERM-CT ties directly to the raw +rail. Read together, this is a push-pull drive into a center-tapped transformer primary: TERM-CT is the center tap, TERM1/TERM2 are the two winding ends, and each end gets alternately pulled to ground by its MOSFET pair while the center tap stays at the supply rail — one classic way to turn a DC rail into an AC square wave. Small note: Q5–Q8 are built on the "IRF740" library deviceset with the value field overridden to "IRF3205" — worth double-checking that the footprint/ratings actually match the part you intend to populate, since those are quite different devices electrically.

Indicator block: R3 (10k) + LED1
R3 feeds LED1 from the regulated 9V rail to ground — a simple power-on indicator, separate from R2 (which only feeds the oscillator's VDD).

How it comes together
IC1 free-runs at a rate set by R1+R4 and C1, producing two antiphase square waves. Each phase is buffered through a discrete push-pull driver (Q1/Q3 or Q2/Q4) to get enough peak current to switch a pair of paralleled IRF3205s quickly. Those MOSFET pairs alternately pull each end of the transformer's center-tapped primary to ground while the center tap sits on the raw DC rail — driving the transformer push-pull at the oscillator's frequency. Given the topology (center-tapped push-pull into a transformer, big paralleled MOSFETs, large bulk caps), this reads as a DC-to-AC square-wave inverter, and R4's trim range is almost certainly meant to dial the switching frequency in to match a target mains frequency (50/60Hz) rather than anything higher — worth confirming against the transformer you're actually driving, since running it off-frequency from what the transformer/load expects is the main thing to get right here.

you-tube video with all files :
https://www.youtube.com/watch?v=C7B8RIV5g_g
cd4047 IRF3205 12V 500W 60Hz Inverter

113 kHz Piezoelectric Disc Driver

Power input block: 15V connector
15V comes in directly onto the main rail and ground, with no series protection diode. Correct-polarity connection matters here, since there's nothing to catch a reversed connection.

Regulated supply block: IC2 (78XX-series) + C4, C5, C6, C7
IC2 steps the 15V rail down to a regulated output that feeds the 555's VCC and reset pins, keeping the timer's supply separate from the higher-current switching rail. C7 (0.1µF) and C4 (100µF) bypass/bulk the regulator's input; C6 (0.1µF) and C5 (100µF) do the same on the output side. Note: the schematic uses a generic 78XX symbol with no specific voltage value set, so the exact regulated voltage isn't confirmable from the file alone — worth checking against your actual populated part.

Oscillator block: IC1 (NE555) + R4 + C3 + C2
This is a self-triggering relaxation oscillator: threshold and trigger are tied together, and that node charges/discharges through the trimmer R4 (10k) directly from the 555's own output, with C3 (10nF) as the timing cap. Discharge is unused. C2 (0.1µF) is the standard control-voltage bypass. R4 is your frequency-trim knob, meant to bring the 555's free-running rate into alignment with the LC tank's resonant frequency below.

Gate-drive block: R1 + R3
R1 (10R) is the gate series resistor from the 555's output, limiting instantaneous gate-charge current and damping ringing in the gate-drive loop. R3 (10k) pulls the gate to ground, keeping Q1 reliably off if the gate is ever left floating.

Resonant output block: Q1 + L1 (330µH) + C1 (0.1µF)
Q1's source is grounded, and its drain sits on a node shared by L1 and C1. L1's other end is wired directly to the 15V rail. When Q1 turns on, current builds through L1 from the rail; when Q1 turns off, that current can't stop instantly, so the drain voltage swings upward and the LC network (L1 together with C1 and the piezo's capacitance, which sit effectively in series from the drain's perspective) goes into its resonant transition — an approximately sinusoidal ring, with the exact shape depending on switching timing, inductor Q, piezo impedance, and how closely the 555's frequency tracks the loaded resonance. C1 couples that ringing drain node out to the PIZO connector.

Indicator block: R2 + LED1
R2 (10k) feeds LED1 from the regulated rail to ground — a simple "board is powered" indicator, unrelated to the oscillator or output stage.

How it comes together
The 555 free-runs at a rate set by R4 and C3, tuned close to the LC tank's resonance. Each cycle, Q1 switches, energy transfers into the tank, the tank rings near its natural frequency, and the direct connection to the 15V rail replenishes the energy the piezo dissipates as it vibrates. It's open-loop throughout — nothing about the piezo's or drain's actual waveform feeds back into the 555; the design's job is simply getting the oscillator frequency and the loaded resonance close enough together that the switching drives the tank efficiently. Since L1 is now 330µH (a real change from whatever value was there when this was last tuned), the resonant frequency has shifted, and the 555's rate via R4/C3 should be re-checked against the tank's new resonance rather than assumed to still be correct.
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you tube video link with all files :
https://www.youtube.com/watch?v=kNJp2BRtzR4
113Khz Water Atomizer Circuit + PCB